説明
説明なし構成
Si02/TEOS -Process: SiO2-SiN- PSG-BSG-BPSG -SMIF: No -Aligner: No -Loaders: One arm robot -Sensors: Wafer detection – cassette door closed -Gas box: 8 stick -Configuration of each process module: One process chamber (SiO2-SiN- PSG-BSG-BPSG) -SW Version: 4.31OEMモデルの説明
The Novellus Concept-One is a PECVD tool that uses plasma-enhanced chemical vapor deposition to deposit various dielectric films on silicon wafers. It can deposit oxide, nitride, oxynitride, PSG and TEOS oxide films. The Concept1 is also a PECVD tool that deposits dielectric films on 6" wafers. It is capable of depositing thick films in excess of 1 um and allows CMOS compatible metals, making it suitable for backend processes. The system deposits on multiple wafers in parallel in a batch-type reactor.ドキュメント
ドキュメントなし
LAM RESEARCH / NOVELLUS
CONCEPT ONE "C1"
検証済み
カテゴリ
PECVD
最終検証： 30日以上前
主なアイテムの詳細
状態：
Used
稼働ステータス:
不明
製品ID：
114673
ウェーハサイズ：
6"/150mm
ヴィンテージ：
1990
Have Additional Questions?
Logistics Support
Available
Money Back Guarantee
Available
Transaction Insured by Moov
Available
Refurbishment Services
Available
同様のリスト
すべて表示
LAM RESEARCH / NOVELLUS
CONCEPT ONE "C1"
カテゴリ
PECVD
最終検証： 30日以上前
主なアイテムの詳細
状態：
Used
稼働ステータス:
不明
製品ID：
114673
ウェーハサイズ：
6"/150mm
ヴィンテージ：
1990
Have Additional Questions?
Logistics Support
Available
Money Back Guarantee
Available
Transaction Insured by Moov
Available
Refurbishment Services
Available
説明
説明なし構成
Si02/TEOS -Process: SiO2-SiN- PSG-BSG-BPSG -SMIF: No -Aligner: No -Loaders: One arm robot -Sensors: Wafer detection – cassette door closed -Gas box: 8 stick -Configuration of each process module: One process chamber (SiO2-SiN- PSG-BSG-BPSG) -SW Version: 4.31OEMモデルの説明
The Novellus Concept-One is a PECVD tool that uses plasma-enhanced chemical vapor deposition to deposit various dielectric films on silicon wafers. It can deposit oxide, nitride, oxynitride, PSG and TEOS oxide films. The Concept1 is also a PECVD tool that deposits dielectric films on 6" wafers. It is capable of depositing thick films in excess of 1 um and allows CMOS compatible metals, making it suitable for backend processes. The system deposits on multiple wafers in parallel in a batch-type reactor.ドキュメント
ドキュメントなし