説明
説明なし構成
J750Ex (512/1024 pins, 8 x HSD200 & 2 DPS)OEMモデルの説明
The J750Ex is a low cost, high efficiency parallel test system for advanced microcontrollers and consumer SoC package test & wafer sort. It is built on the foundation of the J750, one of the most successful test platforms in ATE history. The J750Ex provides highly economical parallel test solutions for high-performance microcontrollers, consumer SoC devices, and digital wafer sort applications. It offers high parallel test configuration with 50% higher throughput and 99% parallel test efficiency. All J750 systems are DIB compatible and can run tens of thousands of J750 test programs. The J750Ex has a range of features including up to 1024 digital pins, 96 device power supplies, and analog test capability, as well as enhanced DFT capability with 196 Gbit scan depth and deep diagnostic capture. It also has a per-pin test architecture, pattern-controlled instrumentation, and flexible site mapping with no slot boundaries. The system is air-cooled and has a “Zero footprint” tester-in-a-test-head design for minimum floor space.ドキュメント
ドキュメントなし
TERADYNE
J750EX
検証済み
カテゴリ
Final Test
最終検証： 30日以上前
主なアイテムの詳細
状態：
Used
稼働ステータス:
不明
製品ID：
113968
ウェーハサイズ：
不明
ヴィンテージ：
2010
Have Additional Questions?
Logistics Support
Available
Money Back Guarantee
Available
Transaction Insured by Moov
Available
Refurbishment Services
Available
同様のリスト
すべて表示
TERADYNE
J750EX
カテゴリ
Final Test
最終検証： 30日以上前
主なアイテムの詳細
状態：
Used
稼働ステータス:
不明
製品ID：
113968
ウェーハサイズ：
不明
ヴィンテージ：
2010
Have Additional Questions?
Logistics Support
Available
Money Back Guarantee
Available
Transaction Insured by Moov
Available
Refurbishment Services
Available
説明
説明なし構成
J750Ex (512/1024 pins, 8 x HSD200 & 2 DPS)OEMモデルの説明
The J750Ex is a low cost, high efficiency parallel test system for advanced microcontrollers and consumer SoC package test & wafer sort. It is built on the foundation of the J750, one of the most successful test platforms in ATE history. The J750Ex provides highly economical parallel test solutions for high-performance microcontrollers, consumer SoC devices, and digital wafer sort applications. It offers high parallel test configuration with 50% higher throughput and 99% parallel test efficiency. All J750 systems are DIB compatible and can run tens of thousands of J750 test programs. The J750Ex has a range of features including up to 1024 digital pins, 96 device power supplies, and analog test capability, as well as enhanced DFT capability with 196 Gbit scan depth and deep diagnostic capture. It also has a per-pin test architecture, pattern-controlled instrumentation, and flexible site mapping with no slot boundaries. The system is air-cooled and has a “Zero footprint” tester-in-a-test-head design for minimum floor space.ドキュメント
ドキュメントなし