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HSD200*8, DPS*2, Z800 workstation CH-1024 TESTER CONFIG: 8 PE + 2 DPS ITEM NO. QUANTITY DESCRIPTION 1 1 J750EX 512 SEMICON TEST SYSTEM NO DPS 2 1 PWR COND 1 MODULE/3 DUMMIES (ENHANCED) 3 2 DEVICE POWER SUPPLY 4 8 J750EX CHANNEL BD CONFIG TO 200MHZ & 64 M 5 8 J750EX DIGITAL SW ENABLED TO 32 MEG LVM 6 8 J750EX DIGITAL SW ENABLED TO 100MHZ 7 1 XW8400 SYSTEM COMPUTER, J750 8 1 KIT 19" LCD MONITOR OPTION 9 1 COMPUTER ANTHRO CART 10 1 MICROSOFT OFFICE 2003 RIGHT-TO-USE LICENSE 11 1 2GB RAM EXTENSION FOR XW8400 12 1 WI 24POS IEEE 488 4 METER LONG 13 1 512 PIN PROBE INTERFACE BOARD 14 1 KLA TESTER SER. DAEMON TESTER 15 1 IG-XL SYSTEM SOFTWARE LICENSE (3.4-3.49) 16 1 1ST YEAR AUL IG- XL SYSTEM LICENSE 17 1 PROBE TOWER, 512 WITH UTILITY BLOCKSOEMモデルの説明
The J750Ex is a low cost, high efficiency parallel test system for advanced microcontrollers and consumer SoC package test & wafer sort. It is built on the foundation of the J750, one of the most successful test platforms in ATE history. The J750Ex provides highly economical parallel test solutions for high-performance microcontrollers, consumer SoC devices, and digital wafer sort applications. It offers high parallel test configuration with 50% higher throughput and 99% parallel test efficiency. All J750 systems are DIB compatible and can run tens of thousands of J750 test programs. The J750Ex has a range of features including up to 1024 digital pins, 96 device power supplies, and analog test capability, as well as enhanced DFT capability with 196 Gbit scan depth and deep diagnostic capture. It also has a per-pin test architecture, pattern-controlled instrumentation, and flexible site mapping with no slot boundaries. The system is air-cooled and has a “Zero footprint” tester-in-a-test-head design for minimum floor space.ドキュメント
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TERADYNE
J750EX
カテゴリ
Final Test
最終検証： 20日前
主なアイテムの詳細
状態：
Used
稼働ステータス:
不明
製品ID：
124810
ウェーハサイズ：
不明
ヴィンテージ：
2010
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